Evgeni Stavinov

2988 Grassina St. #524, San Jose, CA 95136

Telephone: (408) 245-1397

Objective

Challenging position in the areas of FPGA logic design, embedded software, system engineering, networking.

Summary

· Over a decade of diverse design experience: FPGA logic design, embedded software, application development, system engineering

· Design of protocol stacks and IP cores for PCI Express, USB, Wireless USB, Bluetooth, SAS/SATA

· System-level architecture and bring-up of multiple hardware platforms

· Experience in large companies and start-up environments

· Consistent record of innovation and on-time product delivery

Technologies: PCI Express, USB, WirelessUSB, UWB, Bluetooth, 802.11, SAS/SATA

Processors: PowerQUICC, ColdFire, ARM, Xilinx MicroBlaze, x86

FPGAs: Xilinx Virtex/Spartan, Altera Stratix families

Programming Languages: Verilog/VHDL, SystemVerilog, C/C++, ARM/PowerPC Assembly, Perl, TCL, shell scrips

Operating Systems: VxWorks, Embedded Linux, Windows, AMX

Experience

2011 –present:

LeCroy Protocol Solutions Group, Santa Clara, CA

Staff System Design Engineer

· Responsibilities include: researching and architecting next generation test & measurement systems, creating architectural proposals, holding team reviews, evaluating and leading the adoption of new technologies by logic design and embedded software teams

2010 - 2011,

2007 - 2008:

SerialTek, San Jose, CA

Hardware Architect

· Logic and Firmware architecture and implementation of 6Gbs SAS/SATA and USB 3.0 protocol analyzers.

Hardware: Xilinx Virtex-5/6 FPGAs; MicroBlaze processor

Tools: Xilinx ISE, ModelSim, Altium Designer, MS Visual Studio, Java NetBeans

Languages: Verilog, C/C++, Java

2009 – 2010:

Xilinx, San Jose, CA

Staff System Design Engineer

System Integration and Validation Group

· Responsible for porting and validation of ASIC designs on different emulation platforms

Tools: Cadence Palladium, EvE ZeBu, Mentor Veloce, Synopsys Design Compiler, Cadence Conformal LEC, numerous proprietary Xilinx tools

Languages: Verilog/SystemVerilog, TCL, Perl, shell scripting

2004 – 2007:

LeCroy Protocol Solutions Group, Santa Clara, CA

Staff Logic Design Engineer and Technical Lead

· Technical lead of a team of four logic design and firmware engineers to implement protocol analyzer, traffic generator, and device emulation tools for Wireless USB/ MAC, and PCI Express Gen1/Gen2 protocols.

· Defined logic architecture and interfaces for PCI Express Gen1/Gen2 x1-x16 protocol analyzer and traffic generator. Implemented critical parts of FPGA logic for Data Link and Transaction Layers. Ported DDR2 Memory Controller.

· Defined firmware and logic architecture for WirelessUSB/WiMedia MAC protocol analyzer and traffic generator/device emulator.

· Ported reference VxWorks USB, PCI, Ethernet drivers, and Board Support Package to a new board. Implemented Flash and Local Bus drivers for PowerQUICC-II-Pro processor to interface with FPGA.

Hardware: Xilinx Spartan3/Virtex-4 FPGAs; PowerQUICC II Pro, ColdFire processors

Tools: Synplify, Wind River Workbench, Visual Studio .Net

Operating Systems: VxWorks 6.4, Embedded Linux, TargetOS

Languages: Verilog, C/C++, PowerPC Assembly

1999 - 2004:

CATC - Computer Access Technology Corp., Santa Clara, CA.

CATC was a successful company that became public in year 2000 and acquired in 2004.

Positions: Senior Logic Design Engineer, Software Design Engineer.

· FPGA logic design for Bluetooth traffic generator and protocol analyzer products.

· Embedded software design for Bluetooth traffic generator. Ported third-party Bluetooth stack to AMX OS and a new board. Implemented audio drivers. Implemented new Bluetooth protocols not supported by the stack.

· Windows application development for Bluetooth traffic generator and device emulator products. Implemented communication with different SW components of the product using DCOM. Virtualized TCP/IP and COM over Bluetooth.

· Logic design of USB 2.0 IP core for FPGA/ASIC.

Hardware: Xilinx Virtex-II, Altera Stratix FPGAs; ARM7 and 8051-based processors.

Tools: Visual Studio, MetaWare compiler, CodeWarrior IDE

Operating Systems: AMX, Windows

Languages: Verilog, C/C++, MFC, DCOM

Education:

MSEE in Networking, USC - University of Southern California

BSEE, Technion - Israel Institute of Technology (with honors)

Publications

Book: “100 Power Tips For FPGA Designers”, ISBN 978-1461186298

“A Practical Parallel CRC Implementation”, Circuit Cellar magazine, Issue #234, Jan 2010.

“Using Xilinx Tools in Command-line Mode”, Xilinx Xcell Journal issue 74.

Technical Training:

Synopsys SystemVerilog

Wind River VxWorks

Xilinx Advanced FPGA Implementation

Xilinx Introduction to AccelDSP

Embedded Linux

PCI Express Architecture

Windows Device Drivers

US Patents:

Awarded:

“Apparatus and method for synchronization with a communication network by shadowing a page response connection to the network” (patent number 6,757,318)

Pending:

“Wireless analyzer position optimization algorithm”

“Programmable pattern match method and apparatus”

“Protocol Analyzer Architecture for multi-lane serial protocols”

“Passive Bluetooth Test Mode synchronization”

Other:

US Citizen